An important development direction of integrated circuit technology is scaling down the size of the Metal Oxide Semiconductor Field Effect Transistor (MOSFET), whereby to improve integration level and to reduce manufacturing cost. However, it is well-known that the scaling down of the size of the MOSFET will cause short channel effects. With the scaling down of the size of the MOSFET, the effective length of the gate is shrinking, causing the proportion of the depletion layer charges effectively controlled by the gate voltage to diminish. As a result, the threshold voltage drops with the reduction of the channel length.
In a MOSFET, it is usually desirable to increase the threshold voltage of the device to suppress the short channel effects. However, on the other hand, it is also desirable to reduce the threshold voltage of the device to reduce power consumption, especially in applications with low-voltage power supply and applications where both P-type and N-type MOSFETs are used.
A known method for adjusting the threshold voltage is channel doping. However, if the doping concentration of the channel region is increased to increase the threshold voltage of the device, the mobility of carriers will decrease. As a result, the performance of the device will degrade. Moreover, the heavily-doped ions in the channel region may neutralize the ions in portions of the source region and the drain region adjacent to the channel region, such that the ion concentration in these portions will decrease and the device resistance will increases.
Yan et al. proposed in “Scaling the Si MOSFET: From bulk to SOI to bulk”, IEEE Trans. Elect. Dev., Vol. 39, p. 1704, July 1992 that the short channel effects can be suppressed by disposing a ground plane (a grounded back gate) under the insulating buried layer in an SOI (Semiconductor on Insulator) MOSFET.
In case that a plurality of MOSFETs are integrated on a wafer, for each MOSFET, a back gate can be disposed under the insulating buried layer. Different bias electrical fields can be applied to the back gates so that the threshold voltage of each MOSFET can be adjusted individually. However, when the size of the device becomes smaller continuously, there has arisen a problem of ensuring electrical isolation between the back gates of adjacent MOSFET devices. Furthermore, it has become difficult to ensuring electrical isolation between conductive paths of adjacent MOSFET devices.